MSP430F1232IPWR DataSheet
DATASHEET
MSP430F1232IPWR 描述
Single Chip With Easy Interface Between UART and Serial-Port Connector of IBM™ PC/AT ™ and Compatibles Meets or Exceeds the Requirements of ANSI Standard TIA/EIA-232-F and ITU Recommendation V.28 Designed to Support Data Rates up to 120 kbit/s Pinout Compatible With SN75C185 and SN75185 ESD Protection to 2 kV on Bus Terminals Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB) Packages, and DIPs (N)
MSP430F1232IPWR 特点
The MSP430F1232IPWR regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications (Se- ries Stub Termination Logic) for active termination of DDR- SDRAM. The device utilizes an internal operational amplifier to provide linear regulation of VTT without the need for expensive external components. The output stage prevents shoot through while delivering 1.5A continuous current and maintaining excellent load regulation. The MSP430F1232IPWR also in- corporates an active low shutdown pin to tri-state the output during Suspend To Ram (STR) states.
MSP430F1232IPWR 应用
Technical/Catalog InformationMSP430F1232IPWRVendorTexas InstrumentsCategoryIntegrated Circuits (ICs) Program Memory Size