MSP430F123IPWR DataSheet
DATASHEET
MSP430F123IPWR 描述
Test 2 Pin(Internal pull-down pin) Receiver Input 3 with Amp for 0.2Vpp NC Pin(No Internal bonding pin, Fixed to AVSS) Receiver Input 4 with Amp for 0.2Vpp Power-Down Mode Pin H: Power up, L: Power down reset and initialize the control register. Interrupt 0 Pin Interrupt 1 Pin Control Data Input Pin Control Data Output Pin Control Data Clock Pin Chip Select Pin Test 3 Pin(Fixed to AVSS) Transmitter 1 Output Pin Transmitter 2 Output Pin Xtal Osc Enable Pin H : Enable, L : Disable Transmitter 3 Output Pin Digital Power Supply Pin, 4.75 ∼ 5.25V Digital Ground Pin Output Buffer Power Supply Pin, 2.7 ∼ 5.25V Xtal Output Pin Xtal Input Pin External Master Clock Input Pin MCKO1 Disable Pin H : MCKO1 L output, L : MCKO1 output
MSP430F123IPWR 特点
The output pin OUT is connected to input pins VH or VL respectively, depending on the status of the IN pin. When the OE pin is active low, the output is placed in the 3-state mode. The isolation of the output FETs from the power supplies enables VH and VL to be set independently, enabling level- shifting to be implemented. Related to the EL7155, the MSP430F123IPWR adds a lower supply pin VS- and makes VL an isolated and independent input. This feature adds applications flexibility and improves switching response due to the increased enhancement of the output FETs.
MSP430F123IPWR 应用
Technical/Catalog InformationMSP430F123IPWRVendorTexas InstrumentsCategoryIntegrated Circuits (ICs) Program Memory Size