XC17S200APDG8C DataSheet
DATASHEET
XC17S200APDG8C 描述
After Preset Mode inputs have been changed to one of the modes, the next positive-going clock transition changes an internal flip-flop so that the countdown can begin at the second positive-going clock transition. Thus, after an MP (Master Preset) mode, there is always one extra count before the output goes high. Figure 1 illustrates a total count of 3 (8 mode). If the Master Preset mode is started two clock cycles or less before an output pulse, the output pulse will appear at the time due. If the Master Preset Mode is not used, the counter jumps back to the Jam count when the output pulse appears.
XC17S200APDG8C 特点
(5) Nominal capacitance The capacitance is expressed in three digit codes and in units of pico farads (pF). The first and second digits identify the first and second significant figures of the capacitance. The third digit identifies the multiplier. R designates a decimal point.
XC17S200APDG8C 应用
The low-side XC17S200APDG8C driver provides an output pin 8 (FLT) to indicate a high- side (XC17S200APDG8C) or a low-side (XC17S200APDG8C) fault. This output pin is an "open-drain" output. The XC17S200APDG8C low- side driver fault indications are similar to the XC17S200APDG8C high-side driver indications as outlined above. A "graphic" logic diagram of the chipset´s FLT function is presented in Fig.4. Note that this diagram presents the logic of this function at the "low-side" XC17S200APDG8C driver and is not the actual circuit. It describes the combined logic of the "fault logic" and "hi-side fault sense" blocks in both the XC17S200APDG8C and XC17S200APDG8C as shown in Fig. 2 and 3.
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描述
询价
10241
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For example, if a block of data is to be transfer