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XC17S50APDG8C

工厂型号: XC17S50APDG8C
型号类别: 内存
厂商: XILINX
型号: XC17S50APDG8C
批号:
数量: 17877
更新日期: 2011/09/20

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描述

特点

应用

XC17S50APDG8C 描述

    

XC17S50APDG8C 特点

    Hynix XC17S50APDG8C-H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix XC17S50APDG8C-H/L series con- sists of eighteen 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix XC17S50APDG8C-H/L series provide a high performance 8-byte interface in 5.25" width form factor of industry stan- dard. It is suitable for easy interchange and addition.

XC17S50APDG8C 应用

    The input sample period is defined between rising edges of wordclock (WDCLK) input. Nominally, this is a 50% duty-cycle clock at frequency Fs, but it can be a pulse with Ts/256 < pulse-width < Ts (255/256); Ts=1/Fs. Left channel data is presented to the XC17S50APDG8C with rising edge of WDCLK, and right channel data is presented Ts/2 seconds later (when WDCLK falls if 50% duty cycle).
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