xc2c128-7vqg100c DataSheet
DATASHEET
xc2c128-7vqg100c 描述
The ADV7183A has a 5-line, superadaptive, 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required. Video user controls such as brightness, contrast, saturation, and hue are also available within the ADV7183A.
xc2c128-7vqg100c 特点
DAC sample rate clock. It is input for slave mode and output for mas- ter mode. For normal or left-justified type SDI data input, a high in SFDA indicates left channel data, a low in SFDA indicates right chan- nel data. For I2S type, a low in SFDA indicates left channel data, a high in SFDA indicates right channel data.For DSP mode, async pulse in SFDA is followed by two data words, left channel data is fol- lowed by right channel data.
xc2c128-7vqg100c 应用
The XC2C128-7VQG100C includes an on-chip precision voltage reference and an additional power amplifier, capable of driving 300Ω loads differentially up to a level of 6.3V peak-to-peak. The analog section is fully differential, reducing noise and improving the power supply rejection ratio. The data transfer protocol supports both long-frame and short-frame synchronous communications for PCM applications, and IDL and GCI communications for ISDN applications. XC2C128-7VQG100C accepts 2MHz master clock rate, and an on-chip pre-scaler automatically determines the division ratio for the required internal clock.
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描述
询价
10241
11+
PARAMETER Reference Voltage Section Fb Voltage
13752
11+
The floating-point register file is made u
13848
Hardware Reset, active Low. Provides a hardware me
5208
A high on the MASTER RESET (MR) sets all the cont
14048
Addresses and chip enables are registered at risin
16717
The XC5200 Field-Programmable Gate Array Family i
15491
Wiper position programming defaults to midscale a
17695
The CS5381 uses a 5th-order, multi-bit delta-sigma
8886
The mounting area was reduced by mak- ing the tw
13759
The A-to-B enable (CEAB) input must be low in ord
17911
via an RF or an infrared transmission medium upo
4950
Note 2: The maximum power dissipation is dictated
4838
The BRT (Bias Resistor Transistor) contains
4726
The deserializer stays in lock until it cannot de
8877
Output, Pin 14, is suitable for controlling a pow
16463
Description plastic lead chip carrier; 44 leads
11206
OSCS is a system oscillator I/O pin connected to
18010
Design and specifications are subject to cha
17963
The MAX104 features an on-board +2.5V precision b
16545
Output Bit Driver Voltage Supply Ground Output